High Performance, High Capacity Memory Systems and Modules

ABSTRACT

Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

BACKGROUND

Memory systems commonly include a memory controller that communicateswith some number of memory modules via physical connections called“channels.” For data storage, memory modules include dynamic randomaccess memory (DRAM) components. Successive generations of DRAMcomponents have benefitted from steadily shrinking lithographic featuresizes. Storage capacity and signaling rates have improved as a result.

One metric of memory system design which has not shown comparableimprovement is the number of modules one can connect to a singlechannel. Adding a module to a channel increases the “load” on thatchannel, and thus degrades signaling integrity and limits signal rates.The number of modules per memory channel has thus eroded with increasedsignaling rates.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A depicts a memory system 100A in which a motherboard 102 supportsa memory-controller component 105 that communicates with a memory module110 via data link groups 115 and 120, a command-and-address (CA) link125, and a chip-select link 130.

FIG. 1B depicts a memory system 100B in which the same motherboard 102of FIG. 1A is populated with two memory modules 110A and 110B, each in ahalf-width mode.

FIG. 2A depicts a configurable, variable-data-width memory module 200 inaccordance with another embodiment.

FIG. 2B depicts the left side of module 200 of FIG. 2A enlarged andedited for ease of illustration.

FIG. 3A depicts a motherboard 300 in accordance with another embodiment.

FIG. 3B depicts a memory system 315 with a single memory module 200installed in one of the memory-module sockets 310 of motherboard 300 ofFIG. 3A.

FIG. 3C depicts a memory system 325 with a two memory modules 200installed, one in each of the third and fourth sockets 310 ofmotherboard 300.

FIG. 3D depicts a memory system 330 with two memory modules 200installed, one in each of the second and fourth sockets 310 ofmotherboard 300.

FIG. 3E depicts a memory system 335 with a continuity module 320installed in the nearest socket and three memory modules 200 installedin the remaining three.

FIG. 3F depicts a memory system 340 with four installed memory modules200, each of which is configured at initialization to the half-widthmode.

FIG. 3G depicts a memory system 345 that employs an alternativemotherboard wiring pattern.

FIG. 3H depicts a memory system 355 that employs another alternativemotherboard wiring pattern.

FIG. 3I depicts memory system 340 of FIG. 3F omitting some details infavor of showing all nine data-link groups DQu/DQv that extend fromcontroller 305.

FIG. 4 details a portion of memory module 200, introduced in FIGS. 2Aand 2B, highlighting features and connectivity that support widthconfigurability in accordance with one embodiment.

FIG. 5 is a timing diagram 500 illustrating a column read operation forthe four-module memory system 340 FIG. 3F, with module details providedin FIG. 4.

FIG. 6 details an embodiment of address-buffer component 215 of FIG. 2.

FIG. 7 depicts data-buffer component 210 in accordance with oneembodiment.

FIG. 8 depicts a memory system 800 in accordance with one embodiment.

FIGS. 9A-9D depict nibble-wide DQ routing options for an individualmemory channel of memory system 800 of FIG. 8 populated with differentnumbers of modules.

FIG. 9E illustrates memory system 900 of FIGS. 9A-9D, in this instanceshowing the CA (command/address) routing topology.

FIGS. 10A-10C depict nibble-wide DQ routing options for an individualmemory channel of a motherboard 1005 in accordance with anotherembodiment.

FIGS. 11A-11D depict byte-wide DQ routing options for an individualmemory channel of a motherboard 1105 in accordance with anotherembodiment.

FIG. 12 depicts a memory system 1200 similar to system 340 of FIG. 3F,which like-identified elements being the same or similar.

DETAILED DESCRIPTION

FIG. 1A depicts a memory system 100A in which a motherboard 102 supportsa memory-controller component 105 that communicates with a memory module110 via data link groups 115 and 120, a command-and-address (CA) link125, and a chip-select link 130. Motherboard 102 includes twomemory-module sockets, one of which includes module 110 and the other acontinuity module 135. Continuity module 135 includes electrical traces140 that interconnect link groups 115 from controller component 105 withmotherboard traces 145 that extend between the two similar memory-modulesockets. Because of continuity module 135, controller component 105advantageously communicates with memory module 110 via point-to-pointconnections. As detailed below in connection with FIG. 1B, motherboard102 and memory module 110 likewise support point-to-point dataconnections in a two-module configuration. Alternatively, motherboard102 can be used with legacy memory modules, albeit with some capacitylimitations to be discussed below. Resistors 132 can terminate linkgroups as needed to minimize signal reflections.

Module 110 includes a pair of DRAM components 150, a data-buffercomponent 155, and an address-buffer component 160, all of whichcommunicate with controller component 105 via a module interface 165. (Apractical embodiment will likely have far more DRAM components; thisexample is simplified for ease of illustration.) Address-buffercomponent 160, alternatively called a “Registered Clock Driver” (RCD),is coupled to command/address link group 125 and chip-select link group130 from controller component 105 via a primary address interface DCAand primary chip-select interface DCS, respectively. Address-buffercomponent 160 is coupled to each DRAM component 150 via a secondaryaddress interface SCA and secondary chip-select interface SCS, and todata-buffer component 155 via a data-steering interface DS. Dampingresistors can be placed in series with and before each data-buffercomponent 155.

Controller component 105 communicates command and address signals CA andchip-select signals CS to initiate memory transactions (e.g., read andwrite transactions) with module 110. (In general, signals and theirassociated nodes carry the same designations. Whether a given monikerrefers to a signal or a corresponding node will be clear from thecontext.) Address-buffer component 160 interprets (and, in many cases,retransmits to DRAM components 150) these commands, addresses, andchip-select signals as needed to respond to the controller's requests,facilitating data movement between DRAM components 150 and moduleinterface 165 via data-buffer component 155. Point-to-point dataconnections facilitate fast and efficient signaling between controller105 and memory module 110. Memory transactions and point-to-pointsignaling are familiar to those of skill in the art; a detaileddiscussion is therefore omitted for brevity.

Data-buffer component 155 includes two primary data interfaces, coupledto respective link groups 115 and 120 to communicate respective datasignals DQu′ and DQv′, and two secondary data interfaces, one to each ofthe two DRAM components 150. (Each DRAM component 150 can, in someembodiments, represent a stack of DRAM die or DRAM packages, as isfamiliar to those of skill in the art.) Module 110 is in a full-widthmode in this example, in which case address-buffer component 160 issuesa data-steering signal on interface DS that causes data-buffer component155 to provide buffered data paths between two active DRAM component 150and respective link groups 120 and 115. In some embodiments module 110is backward compatible with conventional memory modules, and cancommunicate with controller 105 as a conventional memory module in thefull-width mode. Motherboard 102 is also backward compatible withreadily available memory modules, and can employ a conventional,full-width module in place of module 110. A full-width module can beeither a fixed-width module or a variable-width module programmed to afull-width mode.

FIG. 1B depicts a memory system 100B in which the same motherboard 102of FIG. 1A is populated with two memory modules 110A and 110B, each in ahalf-width mode. Due to the motherboard connectivity, each module isconnected to controller component 105 via only one of link groups 115and 120. Modules 110A and 110B thus exhibit a lower load on the datalink groups than systems in which two modules share the same data links.

In the half-width mode, address-buffer component 160 issues adata-steering signal DS on a like-identified interface that causesdata-buffer component 155 to route all accesses to and from DRAMcomponents 150 through the same primary data interface; the remainingprimary data interface is not used. Rather than selecting both DRAMcomponents 150 for one memory transaction, as in the full-width mode ofFIG. 1A, the address-buffer component 160 on each of modules 110A and110B selects only one DRAM component 150 for each transaction and routesdata to or from the selected DRAM component via data-buffer component155. Address-buffer components 160 control their respective steeringsignals DS and secondary chip-select signals SCS by decoding primarychip-select signals DCS, primary address signals DCA, or both.Address-buffer components 160 and data-buffer components 155 support thedifferent operational modes so that DRAM components 150 can be standard,readily available memory components.

In FIGS. 1A and 1B it is assumed that DQ link groups 115 and 120 operateat or near a maximum practical signaling rate to maximize the databandwidth between controller 105 and the module or modules 110. For bothmodule configurations, the point-to-point connections support theserelatively high data rates. The command and chip-select link groups 125and 130 are point-to-two-point connections that operate at a lower rate.

FIG. 2A depicts a configurable, variable-data-width memory module 200 inaccordance with another embodiment. Module 200 includes eighteen DRAMcomponents 205 on each side, for a total of 36 components. Each DRAMcomponent 205 may include multiple DRAM die or multiple DRAM stackedpackages. Each DRAM component 205 communicates four-bit-wide (x4, or a“nibble”) data in this example, as directed by an address buffer 215that communicates with buffers 205 via secondary command and chip-selectlink groups SCA and SCS. Different data widths and different numbers ofcomponents and dies can be used in other embodiments. Resistors 217 canterminate link groups as needed to minimize signal reflections.

Module 200 includes nine data-buffer components 210, or “data buffers.”Each data-buffer component 210 steers data, at the direction of steeringsignals DS, from four DRAM components 205 to and from two data ports DQuand DQv of a module interface 212. Each DRAM component 205 communicatesx4 data and complementary timing reference signals (e.g., strobesignals), for a total of six data-bus connections. These connections aredetailed in e.g. FIG. 4 and the related text.

Address-buffer component 215 selectively interprets and retransmitscommand, address, and chip-select signals received on primary ports DCAand DCS to control memory components 205 and data-buffer components 210.Addresses associated with the commands identify target collections ofmemory cells (not shown) in components 205, and chip-select signalsassociated with the commands allow address-buffer component 215 toselect individual integrated-circuit DRAM dies, or “chips,” for bothaccess and power-state management. A complementary clock signal (notshown) provides reference timing to module 200. Data-buffer components210 and address-buffer components 215 each acts as a signal buffer toreduce loading on module interface 212. This reduced loading is in largepart because each buffer component presents a single load to moduleinterface 212 in lieu of the multiple DRAM dies each buffer componentserves.

Data-buffer components 210 are “dual-nibble” (x8, or a “byte”) buffersin this example. However, data widths and the ratio of memory components205 to data-buffer components 210 can be different, and some or all ofthe steering and delay functionality attributed to data-buffercomponents 210 can be incorporated into the memory dies or elsewhere inmemory components 205. Module interface 212 connects to one memorychannel, which may be one of a number of memory channels associated witha given controller component.

Each of the nine data-buffer components 210 communicates eight-wide datafor a total of 72 data bits. That is, N*64 data bits are encoded intoN*72 signals, where N is an integer larger than zero (in modern systems,N is usually 1 or 2), where the additional N*8 data bits allow for errordetection and correction. In particular, a ninth data-buffer component210 and related DRAM components 205 are included in this embodiment tosupport eight additional bits used for error checking and correction(ECC). For example, a form of ECC developed by IBM and given thetrademark Chipkill™ can be incorporated into module 200 to protectagainst any single memory die failure, or to correct multi-bit errorsfrom any portion of a single memory die. Data-buffer components 210 cansteer data as necessary to substitute a failed or impaired die. ECCsupport can be omitted in other embodiments.

FIG. 2B depicts the left side of module 200 of FIG. 2A enlarged andedited for ease of illustration. In this example, module 200 is backwardcompatible with what is conventionally termed a “DDR4 LRDIMM chipset.”DDR4 (for “double-data-rate, version 4”) is a type of DRAM die, andLRDIMM (for “load-reduced, dual inline memory module”) is a type ofmemory module that employs a separate system of buffers to facilitatecommunication with the memory dies. Those of skill in the art arefamiliar with both DDR4 memory and LRDIMM modules, so detailedtreatments of these technologies are omitted here. The followingdiscussion highlights aspects of DDR4 LRDIMM circuitry relevant tocertain improvements.

Data-buffer components 210 are disposed across the bottom of module 200to minimize stub lengths and concomitant skew between data bits.Data-buffer components 210 provide load isolation for read, write, andstrobe signals to and from components 205, and each receives acommunication signal COM and select signal SEL that together direct thesteering of data between DRAM component 205 and module interface 212.

The operation of module 200 is consistent with that of LRDIMM servercomponents that employ DDR4 memory. Briefly, address-buffer component215 (“RCD” for “registering clock driver” in the figure) registers andre-drives signals from the memory controller to access DRAM components205. Address-buffer component 215 selectively interprets and retransmitscommands (e.g., in a manner consistent with the DDR4 Specification) andconveys corresponding commands to DRAM components 205 via secondarycommand and chip-select interfaces SCA and SCS[3:0]. The signals forsecondary interfaces SCA and SCS[3:0] are specific to the installedmemory dies, and the timing, format, and other parameters of thosesignals are specified for commercially available dies in a manner wellunderstood by those of skill in the art.

Address-buffer component 215 serves multiple secondary chip-select linksSCS[3:0] to separately select components 205. Address-buffer component215 includes logic 225 to direct primary chip-select informationarriving via primary chip-select interface DCS to these secondarychip-select interfaces.

Module 200 supports the full-width (byte-wide) and half-width(nibble-wide) modes introduced in connection with FIG. 1. data-buffercomponent 210 is illustrated with each of three possible connections, afirst connection 235 used in full- and half-width modes, a secondconnection 240 used only in the half-width mode, and a fourth connection245 used only in the full-width mode. Register 230 can be loaded bylogic 225 during system initialization. In other embodiments, register230 is located elsewhere (e.g., in component 215).

Three depictions of data-buffer component 210 across the bottom of FIG.2B illustrate the different connectivities associated with the modes. Inthe full-width mode, logic 225 issues a command via interface COM to setthe contents of mode register 230 to zero. In this mode, connections 235and 245 together convey byte-wide data DQu/DQv between a selected pairof DRAM components 205 and module interface 212, irrespective of thevalue of select signal SEL from logic 225. Logic 225 derives secondarysignals SCA and SCS[3:0] from primary signals DCA and DCS to read andwrite byte-wide data from and to components 205. In the half-width mode,logic 225 causes data-buffer component 210 to load a one into moderegister 230. Logic 225 then directs information received on primarychip-select interface DCS to secondary chip-select interface SCS toenable a subset of components 205. Logic 225 additionally decodesaddress and chip-select signals Add and CS to selectively assert selectsignal SEL to data-buffer component 210. If signal SEL is a logic zero,data-buffer component 210 directs nibble-wide data to and from one ofthe left-side components 205; if signal SEL is a logic one, data-buffercomponent 210 directs nibble-wide data to and from one of the right-sidecomponents 205. Two modules in the half-width mode can be used togetherto provide byte-wide data in the manner discussed in connection withFIG. 1B. Signal SEL need not be generated by logic 225. The equivalentinformation can be conveyed to data-buffer components 210 by encodingthis information in the command sequence transmitted across the BCOMbus.

FIG. 3A depicts a motherboard 300 in accordance with another embodiment.As detailed below, motherboard 300 supports memory systems in which eachchannel of a memory controller communicates with up to four modules, buteach DQ link group connects to at most two memory modules. Alternativenames for motherboard 300 include mainboard, system board, or logicboard.

Motherboard 300 includes a memory controller 305 and first, second,third, and fourth memory-module sockets 310, or “connectors.” Sockets310 have similar collections of pin groups that provide physicalconnectivity to installed memory or connectivity modules. The number ofpin groups on each socket, reduced here for ease of illustration,includes data pin groups 311, a command pin group 312, and a chip-selectpin group 313.

Motherboard 300 connects controller 305 to each socket 310 via DQ (data)link groups DQu, DQv, DQs, and DQt; a CA (command and address) linkgroup CA, and two CS (chip select) link groups CS1 and CS2. Thesesignals and their respective conductors are collectively part of onememory “channel” 314. Each DQ link group has four DQ data links (anibble), and one complementary timing link (e.g., a strobe signal DQS),for a total of six wired connections. A full memory channel includesadditional pairs of similar DQ link groups, and motherboard 300 mayinclude additional channels, but these resources are omitted here forease of illustration.

Link group DQu connects controller 305 to corresponding pin groups 311on the first and third module sockets 310, and link group DQv extendsfrom controller 305 to the second and fourth module sockets 310. Linkgroups DQs and DQt are not connected to controller 305; rather, linkgroup DQs extends between pin groups 311 on the first and second sockets310 and link group DQt between the third and fourth. Socket connectionsare denoted by curved segments between the link groups and sockets.

Link group CA extends to all four sockets 310, and includes twenty-sixlinks: eighteen A (address), two BA (bank address), two BG (bank group),one ACT (activate), one PAR (parity), and a complementary CLK (clock).Chip-select link group CS1 extends to the first and second modulesockets 310, and link group CS2 to the third and fourth. Each ofchip-select links CS1 and CS2 includes nine links, including five CS(chip select), two ODT (on-die termination), and two CKE (clock enable).The primary CS and CA links operate at one quarter or one half thesignaling rate of the DQ link groups. Each of these links is terminatedwith resistive devices that are matched to or higher than thecharacteristic impedance of the link. The resistive devices can bepassive resistors on motherboard 300 or on a module, or can be activeODT devices that are fabricated in the interface circuitry ofintegrated-circuit components on the modules or elsewhere.

FIG. 3B depicts a memory system 315 with a single memory module 200installed in one of the memory-module sockets 310 of motherboard 300 ofFIG. 3A. Module 200 is statically configured at initialization to enterthe full-width mode. Configuration is accomplished by setting aconfiguration field in mode register 230, but can also be done usinge.g. a configuration pin. Control register 230 can be loaded by a slowsignal interface (an SPD bus, an I2C bus, or something similar), or itcan be loaded by a high speed bus (the CA, CS, or DQ link groups).

Memory controller 305 connects directly to module interface 212 ofmodule 200 via data link group DQv. A continuity module 320 connectslink groups DQu and DQt in series to establish a second set of dataconnections between controller 305 and interface 212.Command-and-address link group CA and chip-select link group CS2 connectdirectly to the fourth socket, and thus to installed module 200.Controller 305 is thus able to communicate byte-wide data with module200. Motherboard 300 is compatible with legacy LRDIMM modules, which canbe used in place of module 200 to provide byte-wide data via eachDQu/DQv link-group pair.

FIG. 3C depicts a memory system 325 with a two memory modules 200installed, one in each of the third and fourth sockets 310 ofmotherboard 300. Each module 200 is statically configured atinitialization to enter the half-width mode. Memory controller 305connects directly to module interface 212 of the nearest module 200 viadata link group DQu, and to module interface 212 of the far module 200via data link group DQv. Link groups CA and CS each connects to bothmodules 200. Controller 305 is thus able to communicate nibble-wide datawith each module 200 concurrently, for combined byte-wide data via eachDQu/DQv link-group pair.

Memory controller 305 is assumed to be compatible with legacy memorysystems in this example. Changes to system BIOS (basic input/outputsystem) firmware may be required to configure modules 200 during systeminitialization and calibration to distinguish between the half-width andfull-width modes.

FIG. 3D depicts a memory system 330 with two memory modules 200installed, one in each of the second and fourth sockets 310 ofmotherboard 300. Each module 200 is statically configured atinitialization to enter the full-width mode. Alternatively, one or bothmodules 200 can be a legacy LRDIMM module. In either case, link groupDQu connects memory controller 305 to the far memory module 200 via DQlink group DQt and a continuity module 320, and to the near memorymodule 200 via DQ link group DQs and a second continuity module 320; andlink group DQv connects memory controller 305 directly to both memorymodules. In effect, both memory modules 200 are connected to a common,byte-wide DQ bus. Command and address link group CA connects to bothmodules, and chip-select link groups CS1 and CS2 connect controller 305to the near and far modules 200, respectively.

FIG. 3E depicts a memory system 335 with a continuity module 320installed in the nearest socket and three memory modules 200 installedin the remaining three. The module 200 nearest controller 305 isconfigured at initialization to enter the full-width mode; the remainingtwo modules 200 are configured in the half-width mode. The two topmost,half-width modules 200 are paired together to collectively communicatebyte-wide data. A continuity module 320 provides signals DQu to thefull-width module.

FIG. 3F depicts a memory system 340 with four installed memory modules200, each of which is configured at initialization to the half-widthmode. The two topmost modules 200 are paired together to collectivelycommunicate byte-wide data, as are the two bottommost modules. Each pairof modules exhibits a lower load on the data link groups than system inwhich four modules share the same data links.

FIG. 3G depicts a memory system 345 that employs an alternativemotherboard wiring pattern. In this example, system 345 includes fourinstalled memory modules 200, each of which is configured atinitialization to the half-width mode. Memory system 345 is similar tosystem 340 of FIG. 3F, except system 345 is based on a motherboard 350in which data link groups DQs′ and DQt′ respectively connect theoutermost module sockets and the innermost sockets. CS link groups CS1′and CS2′ respectively direct chip-select signals to the two outermostand two innermost module sockets.

The wiring topology of motherboard 350 provides approximately half thelength of the partially terminated stub seen from the inner DIMMscompared to FIG. 3F on DQu and DQv nets. The reduction in this stubleads to improved signal integrity and higher possible data transfersalong the bus.

FIG. 3H depicts a memory system 355 that employs another alternativemotherboard wiring pattern. In this example, system 355 includes fourinstalled memory modules 360, each of which is configured atinitialization to the half-width mode. Memory modules 360 are similar tomodule 200, but include data-buffer components 365 and address-buffercomponents 370 that can steer data to either the low- or high-ordernibbles. The motherboard 375 include a data link group DQs″ thatinterconnects the two module sockets closest to controller 305 and adata link group DQt″ that interconnects the two sockets farthest fromcontroller 305. Link groups DQs″ and DQt″ can be used with connectivitymodules, in the manner detailed previously, to provide connectivity insystems with fewer than four modules. Modules 360 can be staticallyconfigured at initialization to steer the data as needed. Otherfunctionally equivalent motherboard wiring topologies can be used.

FIG. 3I depicts memory system 340 of FIG. 3F omitting some details infavor of showing all nine data-link groups DQu/DQv that extend fromcontroller 305. This collection of conductors represents the full widthof memory channel 314. Motherboard 300 and memory controller 305 mayinclude more channels in support of more memory modules 200.

FIG. 4 details a portion of memory module 200, introduced in FIGS. 2Aand 2B, highlighting features and connectivity that support widthconfigurability in accordance with one embodiment. Address-buffercomponent 215 is shown with one of the nine data-buffer components 210and the four DRAM components 205 with which the buffer directlycommunicates. Each DRAM component 205 includes a pair of DRAM dies 400,and four components 205 associated with one data-buffer component 210are distinguished using a two-place alphanumeric designation (A0, A1,B0, and B1). Secondary CA interface SCA, secondary CS interface SCS, andcommunication interface COM each include multiple conductors withassociated signals, to be discussed below. In this example, module 200comprises a PC board, with components 205A0/B0 on one side andcomponents 205A1/205B1 on the other.

Data-buffer component 210 includes two “nibble” data ports DQp[3:0],DQSp[0]± and DQp[7:4], DQSp[1]± on the controller side (or “processor”side), where “DQSp[#]±” specifies two-line complementary strobes; andincludes similar data ports DQ[3:0], DQSp[0]± and DQ[7:4], DQSp[1]± onthe DRAM side. Select signal SEL steers data, and commands issued onlines BCOM[3:0] of communication interface COM direct data and configuredata-buffer component 210 in support of width configurability.Alternatively, address buffer 215 can issue a select command in lieu ofselect signal SEL. Signal BCK± is a complementary clock signal, BCKE isa clock-enable signal that allows data-buffer component 210 to e.g.selectively power its interface circuits for improved efficiently, andBODT controls on-die-termination elements in data-buffer component 210for impedance matching. These signals are generally well documented andunderstood by those of skill in the art, with a few modificationsdetailed below.

Each DRAM component 205 communicates with data-buffer component 210 viaa data-and-strobe port DQ[3:0], DQS ±, and communicates withaddress-buffer component 215 over a secondary bus 425 via portsQA/BODT[#], QA/BCKE[#], QA/BCS[i]; and QRST,QA/BCA[23:0],QA/BCK±.Components 205 are conventional, and their input control signals andports are well documented and understood by those of skill in the art.Briefly, signals QA/BODT[#] control the on-die termination values foreach DRAM component 205; signals QA/BCKE[#] (the “CKE” for“clock-enable”), are used to switch components 205 between active andlow-power states; QA/BCS[i] are chip-select signals that determine whichof components 205, if any, is active for a given memory transaction;QRST is a reset signal common to all components 205; QA/BCA[23:0] arecommand and address ports; and QA/BCK±receive a complementary clocksignal that serves as a timing reference.

At the left in address-buffer component 215, the primary links (fromcontroller 305) are labeled “DCK±”, “DCS[8:0]” and “DCA[23:0]”. In thisconfiguration, chip-select links DCS[3:0] carry the decoded chip-selectinformation for four ranks; link DCS[4] is not used. (In this context, a“rank” is a set of memory dies the controller accesses simultaneously toread and write data.) The “slow signals” that are connected toaddress-buffer component 215 are used for initialization and maintenanceoperations.

Address-buffer component 215 copies commands and addresses on linksDCA[23:0] to links QACA[23:0] and QBCA[23:0] of secondary addressinterface SCA. Address-buffer component 215 also copies chip-selectinformation on the primary links DCS[3:0] to only one of link groupsQACS[3:0] or QBCS[3:0] of secondary interface SCS. The choice betweenlink groups QACS[3:0] and QBCS[3:0] depends upon the value of signalDCS[4] in one embodiment, but other bits might be used for thissub-selection function. Address bit A[17] and bank-group address bitBG[1] are other possibilities.

Component 205A0 is on the front of module 200 and contains two DRAM dies400 connected to respective lines QACS[2,0] of secondary CS interfaceSCS, and component 205A1 is on the back of module 200 and contains twoDRAM dies 400 connected to respective lines QACS[3,1]. Component 205B0is on the front of module 200 and contains two DRAM dies 400 connectedto respective lines QBCS[2,0] and component 205B1 is on the back ofmodule 200 and contains two DRAM dies 400 connected to respective linesQBCS[3,1]. DRAM dies and packages can be stacked. Each site can holde.g. one or two DRAMs. The figure shows a front site and a back site,with two DRAMs per site. Other embodiments support more or fewer diesper site, depending e.g. on the DRAM packaging option.

Component 215 conveys memory component sub-selection information todata-buffer components 210 via select signal SEL, also identified asBCOM[4]. This signal instructs each data-buffer component 210 to accesscomponents 205A[1:0] or 205B[1:0] respectively connected to the low(DQ[3:0]) or high (DQ[7:4]) secondary DQ link groups. Signal BCOM[4] canbe used for other purposes, in addition to this selection function. Forexample, they could be used for initialization, maintenance, and testingoperations, or can be used to encode the select signal.

Primary links DCS[8:0] pass signals DODT[1:0], which control the outputdevice termination of components attached to a DQ link that are notperforming a direct access. For a column write operation, for example,one of signals QACS[3:0] on secondary link SCS is asserted, and theQACA[23:0] secondary CA links carry the column write command and addressinformation. One chip-selected DRAM die 400 will perform the writeaccess in the half-width mode, or two in the full-width mode. The writeaccess enables the ODT termination in the DRAM being accessed.Address-buffer component 215 also provides signals DODT[1:0] of theprimary link group DCS[23:0] as secondary signals QAODT[1:0] andQBODT[1:0] to control the terminations of pairs of unselected DRAM dies400 that share a data-buffer connection with a selected die 400. Readaccesses are treated similarly, but address-buffer component 215 directsdata from the selected dies 400 to the controller via data-buffercomponent 210.

For write or read access, the applied termination values will typicallybe different than the value used by the DRAM performing a write access,because the termination is dampening reflections from theinterconnection stub. In the half-width mode, two dies 400 in theunselected component 205 have their terminations enabled. This is notrequired because no data is to be transferred over the affected link,and does not affect performance.

Primary chip-select links DCS[8:0] include two links (e.g., DCS[1:0])that control the power state (clock enable) of 205 that are notperforming a direct access. For a column read operation to the lower die400 of component 205A0, for example, address-buffer component 215asserts signal QACS[2], and secondary links QACA[23:0] carry the columnread command and address information. In the half-width mode, theselected die alone performs the read access. In the full-width mode, thelower die 400 in component 205B0, also connected to link QBCS[2], islikewise selected and participates in the read access.

Address-buffer component 215 includes a number of circuits that areomitted here. Such circuits may include a phase-locked loop, trainingand built-in self-test (BIST) logic, a command buffer, and a commanddecoder. These and other circuits are well understood by those of skillin the art, and details unrelated to the present disclosure are omittedfor brevity.

FIG. 5 is a timing diagram 500 illustrating a column read operation forthe four-module memory system 340 FIG. 3F, with module details providedin FIG. 4. The primary and secondary CA and CS links use 2T-SDR timingin this example, which means that each bit of information occupies atwo-clock-cycle interval. Command and address signals are carried on theprimary links DCA[23:0] (just “DCA” in FIG. 3F), and command and addressinformation is driven for a two-clock-cycle interval.

In the case of an activation operation, the ACT link of DCA[23:0] isasserted, with a row address carried on the A[17:0] links of link groupDCA[23:0]. In the case of a column read or write operation, the ACT linkis de-asserted, and the column command and the column address arecarried on the A[17:0] links. In either case, the bank-group address iscarried on the BG[1:0] links of DCA[23:0], the bank address is carriedon the BA[1:0] links, and the PAR link contains error-controlinformation.

Address-buffer component 215 copies the command and address on primarylinks DCA[23:0] to secondary links QACA[23:0] and QBCA[23:0], which arepart of secondary command interface SCA illustrated in e.g. FIG. 3F. Thesecondary command and address information is also driven for atwo-clock-cycle interval. When module 200 operates in the half-widthmode, one of the secondary CA link groups can be left un-asserted toreduce power.

In the example in FIG. 5 primary CS link DCS[0] link is asserted andlinks DCS[4:1] are not. The asserted link is enabled only in the secondcycle of the two clock cycle interval it occupies. Primary CS linkDCS[4], used here for component sub-selection, is asserted. Component215 thus copies the chip select information from primary links DCS[4:0]links to secondary links QACS[4:0], leaving secondary links QBCS[4:0]un-asserted. Had link DCS[4] not been asserted, component 215 would havecopied the chip-select information from primary links DCS[4:0] links tosecondary links QBCS[4:0] and left secondary links QACS[4:0]un-asserted.

When two half-width modules are accessed concurrently, both modulesreceive the same CS link group and the same DCS[0] link is asserted.Both modules therefore perform the same column operation. However, theselected number of DRAM components 205 on each module 200 is halved. Theassertion of primary DCS[0] link causes signal QACS[0] to be asserted;the secondary CS signal QBCS[0] is not asserted. These signals can becontrolled by an unused link in the CA link group or CS link group. Inthis example, link DCS[4] is used.

FIG. 6 details an embodiment of address-buffer component 215 of FIG. 2.The primary links and their corresponding signals are designated DCK±,DCS[4:0], DCA[23:0], DODT[l :0], and DCKE[1:0]. The “slow signals” thatare connected to the RCD are used for initialization and maintenanceoperations. An internal mode signal IMODE[0] chooses between wide andnarrow modes, as noted previously. In the wide mode, address-buffercomponent 215 copies command and address bits on primary links DCA[23:0]to secondary links QACA[23:0] and QBCA[23:0], and copies chip-selectinformation on primary links DCS[4:0] to secondary links QACS[4:0] andQBCS[4:0]. In the narrow mode, select signal SEL controls which ofsecondary links QACS[4:0] and QBCS[4:0] are asserted.

Address-buffer component 215 copies termination information on primarylinks DODT[1:0] to secondary links QAODT[1:0] and QBODT[1:0]. Component215 also copies the clock-enable information on primary links DCKE[1:0]to secondary links QACKE[1:0] and QBCKE[1:0].

Component 215 decodes or transfers select signal SEL from the primary CSsignals DCS[4:0]. As noted previously, signal DCS[4] can be used.Alternatively, a dedicated pin SELIN can be added to drive select signalSEL. Signal SEL can also be driven from a number of DCA or DCS linksthat are not otherwise needed by memory module 200 to access the DRAMcomponents. For example, signal SEL can be driven from a signal of theprimary command and address link group DCA[23:0]. Address link A[17] isone possibility. Other links could be chosen using a staticconfiguration value from a control register 600. For example, bank-groupsignal BG[1] could be used for SEL in embodiments with eight banks ofDRAM dies. Select signal SEL can also be driven from a signal from theCS link group. FIG. 6 shows how other DCS links could be chosen using astatic configuration value from register 600. Another alternative is theuse of one of the above sources for the SEL value during an activationoperation (ACT=1). This value can be written into a small memory array605 using e.g. the Rank address (DCS[4:0]) and Bank address(BG[1:0]/BA[1;0]) as an index. This value is then read when a columnread or write (ACT≠0) is performed to the activated bank. This meansthat the controller does not need to keep track of the SEL value afterthe row has been activated.

Address bit A[13] could be used during column read or write operations,essentially doubling the size of an activated row; the activated rowstretches across two different DRAM components in the module. Thisavoids the need of specifying SEL during an activation operation, at thecost of an increase in power.

Control register 600 is set statically at system initialization time.There are several possible options for setting this configuration value.These include: [1] a mode pin(s) on the module interface, [2] decoding avalue received on the primary link groups DCA and DCS, the data linkgroups DQu/DQv, or [3] using a slow signal link (e.g. an SPD bus, an I2Cbus, or something similar) to set a control register.

FIG. 7 depicts data-buffer component 210 in accordance with oneembodiment. The primary DQ interface, which connects to e.g. controller305 via link groups DQu and DQv, includes two six-point connections:low-order data and strobe connections DQp[3:0] and DQSp[0]±, andhigh-order data and strobe connections DQp[7:4] and DQSp[1]±. Thesecondary DQ interface, which connects to components 205, likewiseincludes two six-point connections: low-order data and strobeconnections DQ[3:0] and DQS[0]±, and high-order data and strobeconnections DQ[7:4] and DQS[1]±. The local interface to address-buffercomponent 215 receives communication signals BCOM[4:0], complementaryclock signal BCK±, clock enable BCKE, and on-die termination (ODT)control signal BODT. A pair of registers 700 and 705 capturecommunication signals BCOM[4:0] and present them to logic 710, whichderives therefrom an internal mode signal IMODE, an internal selectsignal ISEL, and read and write signals RD and WR. Mode signal IMODE isstored in mode register 230, which was introduced in connection withFIG. 2. In another embodiment signal IMODE is not decoded fromcommunication signals BCOM[4:0], but is provided from component 215 orelsewhere via a separate connection.

Receivers 720 on the primary and secondary sides of data-buffercomponent 210 buffer and convey incoming data signals to steering logicsteering logic 725. Logic 725 steers the received signals to selectedtransmitters 730 as directed by internal mode signal IMODE and internalselect signal ISEL. Those signals, plus a read signal RD and writesignal WR, selectively enable ones of transmitters 730.

Logic 710 loads register 230 with either a one or a zero at thedirection of address-buffer component 215. Setting signal IMODE to zeroselects the wide mode and to one the narrow mode. In the wide mode,data-buffer component 210 transfers read and write data between thelow-order data and strobe connections on the primary and secondary linkgroups (DQp[3:0]/DQSp[0]± to and from DQ[3:0]/DQS[0]±), and transfersdata between the high-order data and strobe connections on the primaryand secondary link groups (DQp[7:4]/DQSp[1]± to and fromDQ[7:4]/DQS[1]±). These transfers occur in parallel.

In the narrow mode, data-buffer component 210 transfers read and writedata between the low-order data and strobe connections on the primaryand secondary link groups (DQp[3:0]/DQSp[0]± to and fromDQ[3:0]/DQS[0]±), or transfers read and write data between the low-orderdata and strobe connections on the primary link groups and thecorresponding high-order connections on the secondary link groups(DQp[3:0]/DQSp[0]± to and from DQ[7:4]/DQS[1]±). Internal select signalISEL selects between these two transfer cases based on select signal SELon line BCOM[4] from address-buffer component 215.

Clock signal BCK±, enable signal BCKE, and termination-control signalBODT are well understood, and their operations are not altered betweenmodes. The value of mode signal IMODE can be established in variousways, including via [1] an external pin, [2] decoding a value receivedon the BCOM[3:0] links, [3] a control register write duringinitialization, and [4] reading a value from a serial-presence detect(SPD) component and set the register bit. Other methods are possible.

FIG. 8 depicts a memory system 800 in accordance with one embodiment.System 800 includes a central processing unit (CPU) 805 and twenty-fourmemory modules 810 affixed to a motherboard 815. Modules 800 can besimilar to those detailed above in connection with FIG. 2. Memorymodules 810 are collected into groups of four, each connected one of sixmemory channels Ch[6:1]. Each channel supports nine DQu nibbles and nineDQv nibbles, each nibble including four data bits and complementarystrobes. Additionally, CPU 805 can be interchanged with an ASIC, FPGA,GPU, ARM processor or any other IC that supports memory transactionswith modules 810. Motherboard 815 may include any number of passivecomponents, voltage regulators, connectors, etc., that are omitted herefor simplicity.

High-capacity, planar memory systems of this type can suffer signaldegradation due to the physical, horizontal trace lengths used tocommunicate between the memory controller and memory modules. Thissignal degradation can be due to via-trace and trace-to-trace noisecoupling, and insertion losses from metallic and dielectric absorptions.Memory system 800 reduces the trace lengths and associated signaldegradation by allowing memory modules to be inserted on the top andbottom sides of motherboard 815.

FIGS. 9A-9D depict nibble-wide DQ routing options for an individualmemory channel of memory system 800 of FIG. 8 populated with differentnumbers of modules. Continuity modules can be inserted in unused socketsto bridge the nibble-based link groups where the terminating memorymodules alleviate strong signal reflections. Modules 810 are simplifiedto show one of nine data-buffer components 910 and associated DRAMcomponents 205. Data-buffer components 910 are similar to data-buffercomponents 210 of FIGS. 2A and 2B, but are modified to support twohalf-width configurations, one for each of the two nibble-wide primarydata interfaces. Motherboard 815 is shown from the side to separatelyillustrate DQ link-group routing on both sides.

FIG. 9A illustrates a memory system 900 that includes motherboard 815 ofFIG. 8 with a single module 810, two empty sockets 310, and aconnectivity module 320. Data-buffer component 910 is configured in thefull-width mode, and operates much as does the example of FIG. 3B. DQlink groups DQu and DQv each terminate at two module sockets 310.

FIG. 9B illustrates a memory system 915 in which motherboard 815supports two modules 810A and 810B, each module with a data-buffercomponent 910 configured in a different half-width mode. Module 810A isconfigured to communicate over the high-order data and strobeconnections, whereas module 810B is configured to communicate over thelow-order connections. Data-buffer components 910 can be similar todata-buffer components 210, but modified to support the high-orderhalf-width mode. Address-buffer component might also be modified toconvey configuration signals for establishing the mode or modes. Thisoption to select either the high-order or low-order half-width mode foreach module allows for board-level routing flexibility.

The far unused module sockets can be populated with continuity modules320 or otherwise terminated to reduce reflections. For example, atermination module can provide a termination impedance for each DQ andDQS signal line to absorb the signals that reach the unused socket.Termination impedances can be coupled to the same supply voltage as theinstalled modules to mimic the memory-module terminations.

FIG. 9C illustrates a memory system 930 in which motherboard 815supports two modules 810, each module with a data-buffer component 910configured in the full-width mode. Alternatively, modules 810 could beconventional fixed-width modules. The unused module sockets arepopulated with continuity modules 320.

FIG. 9D illustrates a memory system 935 in which motherboard 815supports four modules 810A, 810B, 810C, and 810D, each module with adata-buffer component 910 configured in a half-width mode. Modules 810Aand 810D are configured to communicate over the high-order data andstrobe connections, whereas modules 810B and 810C are configured tocommunicate over the low-order connections. Each data link groupconnects a controller (not shown) to two modules. One skilled in the artwill find that the partially terminated stubs seen on link groups DQuand DQv are now approximately a quarter to a tenth the lengths seen bythe inner memory module relative to those of FIG. 3F. As a result, theODT setting of the idle memory module can be set to open instead ofabsorbing, which leads to lower power consumption. Additionally, thereduction in the stub lengths leads to improved signal integrity andhigher data transfers on the buses.

FIG. 9E illustrates memory system 900 of FIGS. 9A-9D, in this instanceshowing the CA (command/address) routing topology. The depiction ofmemory module 810 omits the DQ buffer and DRAM components in favor ofaddress-buffer component 215. CA link groups extend to sockets 310 in a“two-tee daisy chain,” which alleviates a dip in insertion loss commonto four-drop daisy chain topologies. Termination modules (not shown) canbe included, and address-buffer components 215 can include equalizationcircuitry in support of higher signaling rates.

FIGS. 10A-10C depict nibble-wide DQ routing options for an individualmemory channel of a motherboard 1005 in accordance with anotherembodiment. Considering FIG. 10A first, DQ signals DQu and DQv areconveyed via T-shaped link groups 1010 u and 1010 v, respectively. Athird link group 1015 interconnects two of four module sockets 310, anddoes not connect to the memory controller. In this single-moduleconfiguration, motherboard 1005 is provided with a single module 200,two empty sockets 310, and a continuity module 320. Data-buffercomponent 210 is configured in the full-width mode, and operates much asdoes the example of FIG. 3B. The low-order DQ connections of module 200are coupled to link group 1010 u, and the high-order DQ connections arecoupled to link group 1010 v via link group 1015 and continuity module320. Alternatively, the high -order DQ connections of module 200 couldbe coupled to link group 1010 u and the low-order DQ connections to linkgroup 1010 v.

FIG. 10B illustrates a memory system 1020 in which motherboard 1005supports two modules 200 each configured in the half-width mode. Theunused module sockets can be populated with termination modules. Linkgroup 1015 is not used.

FIG. 10C illustrates a memory system 1025 in which motherboard 1005supports four modules 200 each configured in the half-width mode. Linkgroup 1015 is not used.

FIGS. 11A-11D depict byte-wide DQ routing options for an individualmemory channel of a motherboard 1105 in accordance with anotherembodiment. Considering FIG. 11A first, a memory system 1100 includes amotherboard 1105 on which DQ signals DQu and DQv are conveyed viaT-shaped link groups 1110 u and 1110 v, respectively. A third link group1115 interconnects four module sockets 310, and does not connect to thememory controller. In this single-module configuration, motherboard 1105is provided with a single module 1120, two empty sockets 310, and acontinuity module 320. A DQ component 1125 is configured in a full-widthmode, and operates much as does the example of FIG. 3B. The low-order DQconnections of module 1120 are coupled to link group 1110 u, and thehigh-order DQ connections are coupled to link group 1110 v via linkgroup 1115 and continuity module 320. As explained below, DQ components1125 support a data-forwarding mode that that allows modules 1120 to actas continuity modules in multi-module systems.

FIG. 11B illustrates a memory system 1130 in which motherboard 1105supports two modules 1120 that each communicates full-width data.Address buffers (not shown) selectively control DQ buffers 1125 andassociated memory components in the manner detailed previously. Insteadof or in addition to providing different data widths, however, DQbuffers 1125 support a continuity mode in which the corresponding moduleacts as a continuity module for another module undergoing a memoryaccess. In this example, the low-order DQ connections of the rightmostmodule 1120 are coupled to link group 1110 u, and the high-order DQconnections are coupled to link group 1110 v via link group 1115 and theDQ buffer 1125 of the other memory module 1120. DQ buffers 1125 induce asignaling delay on one DQ nibble in the forwarding mode, and the DQbuffer in the accessed module 1120 can impose the same delay on theother nibble to align the nibbles in time.

FIG. 11C depicts system 1130 of FIG. 11B with the leftmost module 1120undergoing a memory access. In this instance the rightmost module 1120forwards the nibble from link group 1115 to the controller via linkgroup 1110 u. System 1130 otherwise functions as noted above inconnection with FIG. 11B.

FIG. 11D depicts a memory system 1135 in which motherboard 1105 supportsfour modules 1120 that each communicates full-width data. This exampleillustrates an access to the lower left module 1120, which is configuredto communicate full-width data. Data DQv is routed directly to thehigh-order bits of DQ buffer 1125 via link group 111 v, which data DQuis routed to the low-order bits via link group 1110 u, the upper rightmodule 1120, and link group 1115. The DQ buffers 1125 in the remainingtwo modules 1120 disconnect the DQ link groups from the respective DRAMcomponents. Each module 1120 can thus provide full-width data usinganother of the modules for continuity to one of the DQ nibbles.

FIG. 12 depicts a memory system 1200 similar to system 340 of FIG. 3F,which like-identified elements being the same or similar. System 1200includes four installed memory modules 1205, each of which is configuredat initialization to the half-width mode. The two leftmost modules 1200are paired together to collectively communicate byte-wide data, as arethe two rightmost modules. As in earlier examples, only 1/9^(th) of thedata resources are shown for ease of illustration.

System 1200 differs from that of FIG. 3F in that modules 1205 omitdata-buffer components 210. Rather, the functionality of those resourcesis incorporated into DRAM components 1210. With reference to therightmost module 1205, four DRAM components 1210 collectively serve linkgroup DQv in this half-width mode, and can serve two such link groups inthe full-width mode. For example, one module 1205 in the full-width modecould be used in lieu of the one module 200 in the example of FIG. 3B.

The four components 1210 are mounted on both sides of module 1205 inthis embodiment, with exemplary arrangements 1215 and 1220 shown incross-section at the top of FIG. 12. Arrangement 1215 includes twostacks of eight DRAM dies interconnected by e.g. through-silicon vias.Stacks 1210A are on either side of module substrate 1225, and eachincludes a master die 1230 with the requisite data-buffer logic. In theother illustrated alternative arrangement 1220 DRAM components 1210B aretwo-package stacks, one on either side of module substrate. Otheralternative arrangements, with the same or different numbers of dies orpackages, can be used in other embodiments.

In the foregoing description and in the accompanying drawings, specificterminology and drawing symbols have been set forth to provide athorough understanding of the present invention. In some instances, theterminology and symbols may imply specific details that are not requiredto practice the invention.

For example, any of the specific numbers of bits, signal path widths,signaling or operating frequencies, circuits or devices and the like maybe different from those described above in alternative embodiments.

Also, the interconnection between circuit elements or circuit blocksshown or described as multi-conductor signal links may alternatively besingle-conductor signal links, and single conductor signal links mayalternatively be multi-conductor signal links.

Signals and signaling paths shown or described as being single-ended mayalso be differential, and vice-versa. Similarly, signals described ordepicted as having active-high or active-low logic levels may haveopposite logic levels in alternative embodiments.

Circuitry within integrated circuit devices may be implemented usingmetal oxide semiconductor (MOS) technology, bipolar technology or anyother technology in which logical and analog circuits may beimplemented.

With respect to terminology, a signal is said to be “asserted” when thesignal is driven to a low or high logic state (or charged to a highlogic state or discharged to a low logic state) to indicate a particularcondition.

Conversely, a signal is said to be “de-asserted” to indicate that thesignal is driven (or charged or discharged) to a state other than theasserted state (including a high or low logic state, or the floatingstate that may occur when the signal driving circuit is transitioned toa high impedance condition, such as an open drain or open collectorcondition).

A signal driving circuit is said to “output” a signal to a signalreceiving circuit when the signal driving circuit asserts (orde-asserts, if explicitly stated or indicated by context) the signal ona signal line coupled between the signal driving and signal receivingcircuits.

A signal line is said to be “activated” when a signal is asserted on thesignal line, and “deactivated” when the signal is de-asserted.

Additionally, the prefix symbol “/” attached to signal names indicatesthat the signal is an active low signal (i.e., the asserted state is alogic low state).

A line over a signal name may also be used to indicate an active lowsignal. The term “coupled” is used herein to express a direct connectionas well as a connection through one or more intervening circuits orstructures.

Integrated circuit device “programming” may include, for example andwithout limitation, loading a control value into a register or otherstorage circuit within the device in response to a host instruction andthus controlling an operational aspect of the device, establishing adevice configuration or controlling an operational aspect of the devicethrough a one-time programming operation (e.g., blowing fuses within aconfiguration circuit during device production), and/or connecting oneor more selected pins or other contact structures of the device toreference voltage lines (also referred to as strapping) to establish aparticular device configuration or operation aspect of the device. Theterm “exemplary” is used to express an example, not a preference orrequirement.

While the invention has been described with reference to specificembodiments thereof, it will be evident that various modifications andchanges may be made thereto without departing from the broader spiritand scope of the invention. For example, features or aspects of any ofthe embodiments may be applied, at least where practicable, incombination with any other of the embodiments or in place of counterpartfeatures or aspects thereof. Accordingly, the specification and drawingsare to be regarded in an illustrative rather than a restrictive sense.

What is claimed is:
 1. A motherboard comprising: a memory-controllercomponent; a first memory-module socket adjacent the memory-controllercomponent; a second memory-module socket adjacent the firstmemory-module socket on a side of the first memory-module socketopposite the memory-controller component; a third memory-module socketadjacent the second memory-module socket on a side of the secondmemory-module socket opposite the first memory-module socket; a fourthmemory-module socket adjacent the third memory-module socket on a sideof the third memory-module socket opposite the second memory-modulesocket; a first data-link group coupling the memory-controller componentto the first memory module socket and the third memory-module socket,the first data-link group extending past the second memory-modulesocket; and a second data-link group extending past the firstmemory-module socket and the third memory-module socket, the seconddata-link group coupling the memory-controller component to the secondmemory module socket and the fourth memory-module socket.
 2. Themotherboard of claim 1, further comprising a first memory module in thefirst memory-module socket and a second memory module in the secondmemory-module socket, the memory controller to direct a memorytransaction to the first memory module and the second memory module viathe respective first data-link group and the second data-link group. 3.The motherboard of claim 2, further comprising a third memory module inthe third memory-module socket and a fourth memory module in the fourthmemory-module socket, the memory controller to direct the memorytransaction to the third memory module and the fourth memory module viathe respective second data-link group and the first data-link group. 4.The motherboard of claim 2, each of the sockets including a similararrangement of pin groups, including a first pin group and a second pingroup; the first data-link group connected to the first pin group of thefirst socket and the second data-link group connected to the second pingroup of the second socket; the first memory module including a firstdata-buffer component to steer first data from the first memory moduleto the first pin group on the first memory module responsive to a readcommand; and the second memory module including a second data-buffercomponent to steer second data from the second memory module to thesecond pin group of the second memory module responsive to the readcommand.
 5. The motherboard of claim 4, further comprising: a thirdmemory module in the third memory-module socket; and a fourth memorymodule in the fourth memory-module socket; the first data-link groupconnected to the first pin group of the third socket and the seconddata-link group connected to the second pin group of the fourth socket;the motherboard steering data from the third memory module to the firstpin group on the third memory module responsive to the read command andsteering data from the fourth memory module to the second pin group ofthe fourth memory module responsive to the read command.
 6. Themotherboard of claim 1, each of the sockets including a similararrangement of pin groups, including a first pin group and a second pingroup, the first data-link group connected to the first pin group of thefirst socket and the second data-link group connected to the first pingroup of the second socket.
 7. The motherboard of claim 1, each of thesockets including a similar arrangement of pin groups, including a firstpin group and a second pin group, the first data-link group connected tothe first pin group of the first socket and the second data-link groupconnected to the second pin group of the second socket.
 8. Themotherboard of claim 1, further comprising: a third data-link groupextending between the first memory-module socket and the secondmemory-module socket; and a fourth data-link group extending between thethird memory-module socket and the fourth memory-module socket.
 9. Themotherboard of claim 8, further comprising: a memory module in one ofthe first memory-module socket and the second memory-module socket; anda continuity module in the other of the first memory-module socket andthe second memory-module socket; the memory module coupled to thememory-controller component via a data path that includes the thirddata-link group connected in series with the continuity module.
 10. Themotherboard of claim 9, wherein the data path includes the firstdata-link group connected in series with the third data-link group. 11.The motherboard of claim 8, further comprising: a memory module in oneof the third memory-module socket and the fourth memory-module socket;and a continuity module in the other of the third memory-module socketand the fourth memory-module socket; the memory module coupled to thememory-controller component via a data path that includes the fourthdata-link group connected in series with the continuity module.
 12. Themotherboard of claim 11, wherein the data path includes the seconddata-link group connected in series with the fourth data-link group. 13.A memory module comprising: a module interface; memory components,including a first memory component and a second memory component; and anaddress-buffer component having: a primary address interface coupled tothe module interface to receive primary memory addresses expressed asprimary-address bits; a primary chip-select interface coupled to themodule interface to receive primary chip-select information as primarychip-select bits; a first secondary chip-select interface coupled to thefirst memory component; and a second secondary chip-select interfacecoupled to the second memory component; and logic to direct the primarychip-select information to the first secondary chip-select interface anddisable the second secondary chip-select interface responsive to asubset of the primary-address bits and a subset of the primarychip-select bits.
 14. The memory module of claim 13, wherein the logicdisables the second secondary chip-select interface in a first mode andsupports a second mode.
 15. The memory module of claim 14, the logic, inthe second mode, to direct the primary chip-select information to thefirst secondary chip-select interface and the second secondarychip-select interface responsive to the same or a different subset ofthe primary-address bits and the same or a different subset of theprimary chip-select bits.
 16. The memory module of claim 13, wherein thelogic directs the primary chip-select information responsive to a modesignal.
 17. The memory module of claim 16, further comprising moderegister to store the mode signal.
 18. The memory module of claim 16,wherein the logic derives the mode signal from at least one of theprimary-address bits and the primary chip-select bits.
 19. The memorymodule of claim 13, further comprising a data-buffer component coupledbetween the module interface and the memory components, the logiccoupled to the data-buffer component to alternatively connect the firstmemory component and the second memory component to the moduleinterface.
 20. The memory module of claim 19, the data-buffer componentincluding: a first primary data-link interface coupled to the moduleinterface; a second primary data-link interface coupled to the moduleinterface; a first secondary data-link interface coupled to the firstmemory component; and a second secondary data-link interface coupled tothe second memory component; wherein the address-buffer component toissue a signal to the data-buffer component to steer data between thefirst primary data-link interface and one of the first and secondsecondary data-link interfaces, and to disable the other of the firstand second secondary data-link interfaces.
 21. The memory module ofclaim 20, wherein the address-buffer component issues the signal to thedata-buffer component to steer the data in a first mode, and wherein theaddress-buffer component supports a second mode to steer the databetween the first primary data-link interface and the first secondarydata-link interface and between the second primary data-link interfaceand the second secondary data-link interface.
 22. The memory module ofclaim 21, further comprising a mode-select terminal to receive amode-select signal to select between the first mode and the second mode,wherein the mode-select signal initializes at least one of theaddress-buffer component and the data-buffer component and maintains theat least one of the address-buffer component and the data-buffercomponent in the mode during operation.
 23. The memory module of claim22, further comprising a register to store the mode-select signal.